AMATEUR VACUUM TUBE MAKING
BUILDING A HAND HELD GETTER FLASHER
The original getter flasher was a bit large and clumsy, also was marginal in power output. Here we have a unit that is more state of the art than the original. The entire getter flasher is built in one handy box that is easily held while flashing the getter. The weight is about 2 pounds (1 kilo), so it is not a nuisance to hold. The output power is approximately 500 watts so it has ample power to flash the tube getter. Indeed, the power is so great that the flasher must be carefully used to keep from burning out the getter ring.
Note the small size of the unit. There is no external power supply or other connected electronics box. Just a line cord. The unit heats getters to evaporation temperature in a few seconds.
All of the electronic parts for the flasher can be purchased from Mouser for about $100. A few other pieces such as 1/4 inch plastic plate and some plastic screen can be found online.
Before considering this project keep in mind that this is a circuit with many critical design points and significant deviation from the design shown here may result in the unit not working or in unreliable operation.
IMPORTANT NOTE!: THIS IS NOT A GENERAL PURPOSE INDUCTION HEATER! IT IS SPECIFIED ONLY FOR FLASHING GETTERS IN VACUUM TUBES WHICH IS A SHORT DURATION OPERATION. OPERATING THE UNIT FOR LONGER THAN 10 SECONDS OUT OF EACH FEW MINUTES WILL RESULT IN OVERHEATING AND FAILURE.
ABSOLUTELY NO GUARANTEE AS TO THE SAFETY OR SUITABILITY OF THIS DESIGN IS MADE. DANGEROUS VOLTAGES ARE PRESENT AND CAN CAUSE PERSONAL INJURY! BUILD IT AT YOUR OWN RISK!
HOW IT WORKS:
Examine the block diagram below.
The power amp operates with rectified line voltage that is not filtered to produce DC. Thus, the output of the power amp is a full wave rectified pulse of the line frequency that is pulsing at the induction frequency of 500 to 600 khz. This eliminates the bulky filter capacitors required to produce pure DC and makes it possible to drastically reduce the stress on the amplifier FETs.
The major cause of failure in this kind of instrument is out-of-bandwidth spikes causing excessive voltage or current through the power FETs. To eliminate these spikes, the circuit is triggered only when the line voltage is very low, a few volts. Thus the stress on the FETs in startup of the circuit is very low so fails due to spikes if the power is suddenly applied at full line voltage are eliminated.
The high frequency RF signal is generated by a 555 timer I.C. that is connected to produce a 50% duty cycle square wave output. The oscillator operates continuously. The output of the oscillator is converted to two gated signals that are 180 degrees out of phase. These two signals feed the gate driver.
To gate the signals on when the activate button is pressed, the line voltage must first be sampled. If the voltage is above a few volts, the circuit will wait until the voltage drops again. (one half cycle of power frequency) Then the gate flip flop is triggered and enables the output signals to reach the driver. By activating the circuit in this way, no high powered switching is involved and very importantly the gate signal is enabled only when the line voltage is low, thus reducing the spike current into the amplifier FETs.
The gates of the amplifier FETs must be driven very strongly to get reasonable efficiency. If the FETs are not switched quickly, there will be excessive heat developed which can cause FET failure. To drive the FET gates at 500 khz, it takes considerable power because of the large input capacitance of the FET. The drive current is typically an amp per FET at 12 volts. That is 12 watts per FET just in drive power! This tremendous drive power is only present at the moment of switching of the FET. Once the FET is switched on or off, the drive power drops to a very low level. But the driver must be capable of the high drive power.
To develop this power a two stage driver takes the CMOS output of the gate IC and first increases the drive to about 100 milliamps to drive the input capacitance of the driver FETs. These FETs are picked to have lower input capacitance than the main power amp FETs. Since the duty cycle of the system is short, only 10 seconds or so active at a time, no heat sinks are required on the driver FETs.
The output of the driver is direct connection for the low end amplifier FET. A 5 ohm resistor limits the peak current into the FET thus reducing somewhat the power dissipation in the gate structure.
The high side driver must be isolated for the line voltage because the source connection of the high side FET is the output, which is switching at 120 volts at 500 khz during operation. This isolation is provided by a small transformer that has suitable coupling at the 500 khz switching frequency. The transformer has negligible coupling at lower frequencies so there is an inherent limit to the low frequency spikes that can be passed. This affords another safeguard to the amplifier FETs by limiting the maximum per cycle on-time the amplifier FET can experience.
The output of the power amplifier is coupled to the induction tuned circuit. This is a high Q resonant circuit that resonates near 500 khz. The 555 oscillator has a frequency control that affords about 200 khz of variation so the exact resonant frequency can be set. The output of the power amplifier is limited to approximately 10 amps by the ratings of the FETs. Thus, a means of increasing the current to the hundred or more amps in the induction coil is necessary. This is done via the coupling capacitors. The capacitors are divided into two parts for an important reason. By placing a capacitor in both the common lead and the feed lead of the circuit there is no direct connection to the output coil to the line voltage. This significantly reduces the shock hazard of the unit that would be present if the common lead was directly connected to the tuned circuit.
The simple capacitive coupling in this manner can theoretically match any two impedances. Of course there are significant practical limitations but fortunately these limitations are not within the operating parameters of the flasher. By choosing the values of the coupling capacitors any drive level up to 10 amps can be selected. 10 amps at 120 volts is 1200 watts drive, which is far beyond reasonable for a getter flasher! So the drive level is picked to deliver around 400 to 500 watts output, which is around 5 to 6 amps from the power line at 120 volts. The circuit works fine at 220 volts line input if the capacitors are adjusted for the proper power output. The only other change for 220 volt operation is the transformer for the 12 volt power supply, which will need a 220 volt primary.
Here is the circuit diagram of the flasher. It consists of two parts, the oscillator-driver and the output amplifier.
Power input from the mains is through a standard PC type power line connector. This allows the power cord to be removed so the unit is easier to store. There is no power switch for a reason. It is important to unplug the unit when you are done using it so it has no chance of being accidently switched on, which could cause it to overheat and burn out.
Power to the oscillator is developed by a simple rectifier on a 10 volt transformer. The unloaded voltage output is about 14 volts and the operating voltage drops to about 11 volts. Regulation is not necessary for this circuit. The large filter capacitor smoothes out the ripple to an acceptable value.
The power line frequency sample for the trigger circuit is derived from the 12 volt rectifier by isolating the rectifier output from the filter capacitor with a series diode. All are Schotky for low voltage loss.
The oscillator is a CMOS version of the 555 timer I.C. The standard 555 is not stable at frequencies above about 200 khz so the CMOS version is necessary. The circuit is connected to give a 50% duty cycle output. The frequency is controlled by a potentiometer that is accessible through the side of the case. It is not necessary to have phase locked loops and other complicated circuitry to keep the frequency matched to the output tuned circuit. A quick adjustment of the frequency knob when the unit is operating is all that is necessary. Keep designs simple for best results!
The gate driver is inverting so it is desired to have the gated input signal at a high level when the gate signal is off. Thus a nand gate is used to control the signal. One section of the nand is used to invert the signal to get the opposite phase. The second section has a slight delay produced by the resistor and the 100pf capacitor. This allows precise setting of the dead time between the two phases so the output power FETs will never both be switched on at the same time.
The triggering of the circuit is locked to the line frequency. The full wave rectified signal from the rectifier is applied through clamping diodes to the base of the transistor. Note that the transistor will be pulled to saturation for the majority of the line waveform. Only when the rectified line voltage is near zero will the base be pulled low to allow the collector to deliver a clock pulse to the D flip flop clock input. Thus, if the activate switch is pressed any time other than when the line voltage is near zero, the circuit will not generate a clock pulse until the voltage drops again. This prevents the gate from activating when the power voltage is high, thus limiting the startup surge current through the power FETs. The gate will remain active until the button is released thus applying the reset to the D flip flop.
The outputs of the gate IC are amplified by emitter follower transistors to get the high drive current required for driving the gate driver FETs at the 500 khz rate. This can take a hundred milliamps current which is beyond the capability of the IC itself. The gate driver FETs are connected in a complimentary pair configuration which provides rail to rail drive at very low impedance to provide the amp current drive for the output amplifier FETs. These FETs have over 2000 pf gate capacitance which must be driven at sub-microsecond rates from cutoff to full on at the 500 khz rate. This takes the 1 amp surge current to keep the transition times sharp for minimum losses in the FETs.
The upper amplifier FET must have its gate drive isolated from the rest of the circuit since it must drive the gate in respect to the source terminal which on that FET is the output. A pulse transformer is used to derive this signal. A 1:2 ratio transformer is used because only half of the signal will be available due to the transformer action centering the output voltage around zero. The signal is capacitive coupled to the FET gate which provides a solid 12 to 15 volt drive signal.
OUTPUT AMPLIFIER DIAGRAM
Refer to the output amplifier schematic on the next page.